Exemplary embodiments of the present invention relate to a semiconductor designing technology, and more particularly, to a write path of a synchronous semiconductor memory device.
A semiconductor memory device such as Dynamic Random Access Memory (DRAM) receives a write data from a chipset, e.g., a memory controller, and outputs a read data to the chipset. In case of a synchronous semiconductor memory device, both chipset and memory are synchronized with a system clock to be operated. However, when a data is transferred from a chipset to a semiconductor memory device, the load and trace/track of the data signal are different from those of the system clock and skew may occur between the data and the system clock.
To reduce the skew between the data and the system clock, a data strobe signal DQS is transferred along with the data when the data is transferred from the chipset to the semiconductor memory device. The data strobe signal DQS is called an echo clock and it may have the same load and trace of the data signal. Therefore, when the semiconductor memory device processes the data based on the data strobe signal DQS, skew occurring in plural memories due to the difference in their positions from a circuit transmitting the system clock may also be minimized. Meanwhile, during a read operation, the semiconductor memory device transfers a read DQS to the chipset along with the read data.
FIG. 1 a circuit diagram illustrating a write path of a conventional synchronous semiconductor memory device.
Referring to FIG. 1, the write path of the conventional synchronous semiconductor memory device includes a DQS input buffering unit 110, a data strobe falling pulse (DSFP) generation unit 120, a DQS buffer disable signal generation unit 130, a data alignment unit 140, a GIO write driving unit 150. The DQS input buffering unit 110 buffers a data strobe signal DQS in response to a DQS buffer disable signal DISABLE_DQS. The DSFP generation unit 120 receives an output signal of the DQS input buffering unit 110 and generates a data strobe falling pulse DSFP which corresponds to a falling edge of the data strobe signal DQS. The DQS buffer disable signal generation unit 130 generates the DQS buffer disable signal DISABLE_DQS in response to the data strobe falling pulse DSFP, a data strobe termination signal DIS_DSP, and a write pulse WRITE_STATE. The data alignment unit 140 aligns input data Din transferred from a data input buffer (not shown) in response to the data strobe falling pulse DSFP. The GIO write driving unit 150 synchronizes aligned data ALGN_R0, ALGN_R1, ALGN_F0, and ALGN_F1, which are outputted from the data alignment unit 140, with a data input clock DINCLK and transfers synchronized data to global data buses GIO_Q0, GIO_Q1, GIO_Q2 and GIO_Q3.
Herein, the data strobe termination signal DIS_DSP is a signal which pulses to a logic high level after a time corresponding to a burst length (BL) passes from a moment when a write command is applied. The write pulse WRITE_STATE is a signal which pulses to a logic low level when a write command is applied. The write pulse WRITE_STATE is enabled to a logic low level before an internal write signal INT_WT (refer to FIG. 2) is enabled. Also, the data input clock DINCLK is a signal which pulses to a logic high level after a certain time in consideration of a write latency WL from a moment when a write command is applied.
Meanwhile, the DQS buffer disable signal generation unit 130 includes an AND gate AND1, a pull-up PMOS transistor MP1, a pull-down NMOS transistor MN1, and a latch INV1 and INV2.
The AND gate AND1 receives the data strobe falling pulse DSFP and the data strobe termination signal DIS_DSP as its input. The pull-up PMOS transistor MP1 includes a source coupled with a power source voltage VDD terminal and a drain coupled with an output terminal N1 of the DQS buffer disable signal generation unit 130, and receives the write pulse WRITE_STATE as a gate input. The pull-down NMOS transistor MN1 includes a source coupled with a ground voltage VSS terminal and a drain coupled with the output terminal N1 of the DQS buffer disable signal generation unit 130, and receives an output signal of the AND gate AND1 as a gate input. The latch INV1 and INV2 latches a signal on the output terminal N1 of the DQS buffer disable signal generation unit 130.
The data alignment unit 140 includes an inverter INV3, a first D-flipflop 142, a second D-flipflop 144, a third D-flipflop 146, and a fourth D-flipflop 148. The inverter INV3 receives the data strobe falling pulse DSFP as its input. The first D-flipflop 142 transfers the input data Din in response to a falling edge of the output signal of the inverter INV3. The second D-flipflop 144 transfers the aligned data ALGN_R1 outputted from the first D-flipflop 142 in response to the falling edge of the output signal of the inverter INV3. The third D-flipflop 146 transfers the input data Din in response to the falling edge of the output signal of the inverter INV3. The fourth D-flipflop 148 transfers the aligned data ALGN_F1 outputted from the third D-flip-flop 146 in response to the falling edge of the output signal of the inverter INV3.
Also, the GIO write driving unit 150 includes a first GIO write driver 152, a second GIO write driver 154, a third GIO write driver 156, and a fourth GIO write driver 158. The first GIO write driver 152 synchronizes the aligned data ALGN_R0 outputted from the second D-flipflop 144 with the data input clock DINCLK and transfers the synchronized data to a first global data line GIO_Q0. The second GIO write driver 154 synchronizes the aligned data ALGN_R1 outputted from the first D-flipflop 142 with the data input clock DINCLK and transfers the synchronized data to a second global data line GIO_Q1. The third GIO write driver 156 synchronizes the aligned data ALGN_F0 outputted from the fourth D-flipflop 148 with the data input clock DINCLK and transfers the synchronized data to a third global data line GIO_Q2. The fourth GIO write driver 158 synchronizes the aligned data ALGN_F1 outputted from the third D-flipflop 146 with the data input clock DINCLK and transfers the synchronized data to a fourth global data line GIO_Q3.
FIG. 2 is a timing diagram of the circuit shown in FIG. 1.
Referring to FIG. 2, first, when a write command is applied, the semiconductor memory device receives a data DQ along with a data strobe signal DQS. FIG. 2 shows a case where write commands are consecutively applied (BL=4). A signal ‘INT_WT’ denotes an internal write signal generated upon receipt of a write command.
Meanwhile, the DSFP generation unit 120 generates the data strobe falling pulse DSFP which is enabled to a logic high level at every falling edge of the data strobe signal DQS, and the data alignment unit 140 outputs the aligned data ALGN_R0, ALGN_R1, ALGN_F0, and ALGN_F1 at a rising edge of the data strobe falling pulse DSFP.
When both of the data strobe falling pulse DSFP and the data strobe termination signal DIS_DSP become logic high levels at the end of the data input, the DQS buffer disable signal generation unit 130 makes the DQS buffer disable signal DISABLEDQS transition to a logic low level. As a result, the DQS input buffering unit 110 is disabled and stop receiving the data strobe signal DQS.
Meanwhile, the aligned data ALGN_R0, ALGN_R1, ALGN_F0, and ALGN_F1 are synchronized with the data input clock DINCLK and transferred by the first to fourth GIO write drivers 152, 154, 156 and 158 to the first to fourth global data lines GIO_Q0, GIO_Q1, GIO_Q2 and GIO_Q3.
However, a one-time ringing may occur frequently when the data strobe signal DQS toggles and goes back to a high impedance (Hi-Z) state after its last falling edge. This phenomenon is referred to as a write postamble ringing. To be specific, the phenomenon means that after the data strobe signal DQS finishes its toggling, it does not go back to the high impedance (Hi-Z) state but transitions due to noise.
FIG. 3 is a timing diagram of the circuit shown in FIG. 1 when the write postamble ringing phenomenon occurs.
Referring to FIG. 3, it may be seen that the ringing occurs when the toggling data strobe signal DQS goes back to the high impedance (Hi-Z) state after its last falling edge.
If the write postamble ringing phenomenon occurs before the DQS buffer disable signal DISABLE_DQS transitions to a logic low level, the DSFP generation unit 120 recognizes it as a falling edge of the data strobe signal DQS and a small glitch may occur in the data strobe falling pulse DSFP.
The values of the aligned data ALGN_R0, ALGN_R1, ALGN_F0, and ALGN_F1 are changed early due to the glitch, and accordingly an erroneous data is synchronized with a rising edge of the data input clock DINCLK and an undesired data may be loaded on the first to fourth global data lines GIO_Q0, GIO_Q1, GIO_Q2 and GIO_Q3, which is a failure.
In other words, in a structure where the DQS input buffering unit 110 is controlled as the DQS buffer disable signal DISABLE_DQS is fed back, a moment when the DQS buffer disable signal DISABLE_DQS is enabled becomes a moment when the DQS input buffering unit 110 is disabled after all. Therefore, there are concerns in the timing that the glitch occurring in the data strobe falling pulse DSFP may be used before the DQS input buffering unit 110 is disabled. Due to such timing, the values of the aligned data ALGN_R0, ALGN_R1, ALGN_F0, and ALGN_F1 are changed early and undesired data may be loaded on the first to fourth global data lines GIO_Q0, GIO_Q1, GIO_Q2 and GIO_Q3, which is problematic.
The above-described problem may occur not only in the case where write commands are consecutively applied but also in a case where a write command is applied alone.